Time to digital converters (TDCs) are designed to generate a digital representation of a time interval elapsing between two events. A TDC converts a time interval directly to a digital code for any subsequent processing.
Clocked delay line time to digital converters (TDCs) or flash analog to digital converters (ADCs) are a couple of examples of very fast thermometer-coded devices. For such devices the propagation delays may be in the region of 20-30 picoseconds as seen for example in deep sub-micron (DSM) inverters. However, when sampling the state of the delay line on the clock edge, there is a need for improving reliability of the devices. For example, metastability is possible where the sampled state of one or more of the line taps is undefined (neither high nor low). Thus, the signal can be within an undesired state. This may cause an error in the thermometer code.
In current known TDCs, and equivalently in flash ADCs, an error code often results in a waste of the appropriate conversion cycle. For example, when an erroneous code is passed out, it is a waste of a complete valid conversion cycle. Consequently it causes errors in the output signal.
In cases where the output code addresses an information lookup table, more than one address may be looked up causing the lookup table output to be in an unknown (and undesired) state. There is therefore a need in the art for techniques for improving reliability of thermometer coded lines without substantially producing false alarms or wrong results.